B K Basu
Articles written in Proceedings – Section A
Volume 45 Issue 4 April 1957 pp 231-239
This paper describes the logical circuits which have been incorporated in the Input-Outpur unit of a pilot electronic digital computer. The unit is used to feed the input data into the calculator from a punched tape through a Photo-electric tape reader and to print out the results, after computation, by standard teletype equipment.
Volume 46 Issue 5 November 1957 pp 354-359
The speed of operation of double rank counters can be increased by a suitable modification of the gating logic now being used. The improvement in speed, predicted on theoretical grounds, has been experimentally verified. The prescribed logic enables the use of both the ranks of the counter to advantage, one rank counting in the normal, and the other in the reverse fashion.
Volume 53 Issue 1 January 1961 pp 44-58
The T.I.F.R. computer is a parallel, binary, asynchronous single address machine. The arithmetic unit consists of a Memory Register, two (double rank) shift registers, the Accumulator and the M.Q. Register respectively, an Adder and a pair of True/Complement gates. A carry bypass logic is described which reduces the maximum carry delay time by a factor of 1/3. The maximum carry delay time for 40 bits is 3