Articles written in Sadhana
Volume 41 Issue 12 December 2016 pp 1369-1380
‘‘Sequential pattern mining’’ is a prominent and significant method to explore the knowledge and innovation from the large database. Common sequential pattern mining algorithms handle static databases.Pragmatically, looking into the functional and actual execution, the database grows exponentially thereby leading to the necessity and requirement of such innovation, research, and development culminating into the designing of mining algorithm. Once the database is updated, the previous mining result will be incorrect, and we need to restart and trigger the entire mining process for the new updated sequential database. To overcome and avoid the process of rescanning of the entire database, this unique system of incremental mining of sequential pattern is available. The previous approaches, system, and techniques are a priori-based frameworks but mine patterns is an advanced and sophisticated technique giving the desired solution. We propose and incorporate an algorithm called STISPM for incremental mining of sequential patterns using the sequence treespace structure. STISPM uses the depth-first approach along with backward tracking and the dynamic lookahead pruning strategy that removes infrequent and irregular patterns. The process and approach from the root node to any leaf node depict a sequential pattern in the database. The structural characteristic of the sequence tree makes it convenient and appropriate for incremental sequential pattern mining. The sequence tree also stores all the sequential patterns with its count and statistics, so whenever the support system is withdrawn or changed, our algorithm using frequent sequence tree as the storage structure can find and detect all the sequential patternswithout mining the database once again.
Volume 47 All articles Published: 3 April 2022 Article ID 0065
This paper presents the design, fabrication and packaging of RF MEMS switches that have CPWconverted- to-microstrip RF interface at the die level. With microstrip input and output ports the packaging of the dies become greatly simplified, doing away with the need for having off-chip matching and RF transition components inside the package. Two designs are presented, each based on a different philosophy for conversion of the inherent CPW version of the chip to microstrip planar transmission line; i) conversion to microstripthrough RF matching, ii) CPW to microstrip on-chip via less transition. Detailed 3D EM simulation based studies were carried out to arrive at the final RF layouts. The switches were fabricated using the silicon on glass architecture and packaged in hermetic RF packages at 1 atm N2. Wafer level and post packaging test methods are described. Over the range DC to 10 GHz, the worst case packaged device insertion loss, return loss and isolation are -1.2 dB, -13 dB, -37.5 dB for the first design variant of the switch and are -1.2 dB, -11 dBand -30 dB respectively for the second design variant. The typical pull in voltage is 50 V.