To meet the demand for low-voltage/low-power and high speed analog-to-digital convertors, a new fully differential double-tail dynamic comparator is proposed. To reduce the power dissipation and speed up the comparison process, charge sharing technique has been used in the latch stage of the proposed dynamiccomparator. In addition, differential pair and double-tail dynamic comparator topologies are combined to minimize the offset voltage. The proposed dynamic comparator has worst case delay of 0.219 ns, power dissipation of 156.3 lW and offset voltage of 0.184 mV with 1r deviation of 7.65 mV. The proposed dynamiccomparator has been simulated in 0.18 lm CMOS technology with supply voltages of ± 0.75 V using Cadence virtuoso analog design environment