Articles written in Sadhana

    • High-speed, low-power and low-offset fully differential double-tail dynamic comparator using charge sharing technique


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      To meet the demand for low-voltage/low-power and high speed analog-to-digital convertors, a new fully differential double-tail dynamic comparator is proposed. To reduce the power dissipation and speed up the comparison process, charge sharing technique has been used in the latch stage of the proposed dynamiccomparator. In addition, differential pair and double-tail dynamic comparator topologies are combined to minimize the offset voltage. The proposed dynamic comparator has worst case delay of 0.219 ns, power dissipation of 156.3 lW and offset voltage of 0.184 mV with 1r deviation of 7.65 mV. The proposed dynamiccomparator has been simulated in 0.18 lm CMOS technology with supply voltages of ± 0.75 V using Cadence virtuoso analog design environment

    • High slew rate and low output resistance class-AB flipped voltage follower cell with increased current driving capability


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      The paper proposes a class-AB flipped voltage follower (FVF) cell, in which the bulk-driven transistor is used as an input transistor with a replica-biased scheme to eliminate the DC level shift while a cascoding transistor is used to reduce the output resistance. The proposed FVF cell has several advantages suchas low output resistance, approximately unity voltage gain, high symmetrical slew rate, high current sourcing capability, high current sinking capability and wide bandwidth. The proposed FVF cell has been simulated inCadence Virtuoso Analog Design Environment using BSIM3v3 180 nm CMOS technology with a power supply voltage of 1.2 V.

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