Articles written in Sadhana

    • High-speed, low-power and low-offset fully differential double-tail dynamic comparator using charge sharing technique


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      To meet the demand for low-voltage/low-power and high speed analog-to-digital convertors, a new fully differential double-tail dynamic comparator is proposed. To reduce the power dissipation and speed up the comparison process, charge sharing technique has been used in the latch stage of the proposed dynamiccomparator. In addition, differential pair and double-tail dynamic comparator topologies are combined to minimize the offset voltage. The proposed dynamic comparator has worst case delay of 0.219 ns, power dissipation of 156.3 lW and offset voltage of 0.184 mV with 1r deviation of 7.65 mV. The proposed dynamiccomparator has been simulated in 0.18 lm CMOS technology with supply voltages of ± 0.75 V using Cadence virtuoso analog design environment

    • High slew rate and low output resistance class-AB flipped voltage follower cell with increased current driving capability


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      The paper proposes a class-AB flipped voltage follower (FVF) cell, in which the bulk-driven transistor is used as an input transistor with a replica-biased scheme to eliminate the DC level shift while a cascoding transistor is used to reduce the output resistance. The proposed FVF cell has several advantages suchas low output resistance, approximately unity voltage gain, high symmetrical slew rate, high current sourcing capability, high current sinking capability and wide bandwidth. The proposed FVF cell has been simulated inCadence Virtuoso Analog Design Environment using BSIM3v3 180 nm CMOS technology with a power supply voltage of 1.2 V.

    • A novel low-input-resistance, high-output-resistance and widebandwidth current mirror using class-AB FVF cell


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      A novel low input and high output resistance current mirror using class-AB FVF cell is presented in this paper. In the proposed current mirror, class-AB cascoded FVF cell acts as a current sensing cell and results in low input resistance of the proposed current mirror. The proposed current mirror uses a regulated cascodeoutput stage to enhance its output resistance. The various other advantages offered by the proposed current mirror are large current mirroring range with high accuracy, low THD, and wide bandwidth. The physical layout of the proposed current mirror has been designed in the Cadence tool. The post-layout simulation results have also been demonstrated to validate its performance.

    • New high frequency memristorless and resistorless meminductor emulators using OTA and CDBA


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      In this paper, new meminductor emulators have been proposed using operational transconductance amplifiers (OTA), a current differencing buffered amplifier (CDBA) and two grounded capacitors. Most meminductor emulators reported in the literature use memristor and resistor in their design but proposedemulators are memristor-less and resistor-less. The proposed emulators are designed for both decremental/ incremental configurations of grounded and floating types of meminductors. The operating frequencies of the proposed emulators are extended up to 2 MHz for both grounded and floating configurations. The proposed circuits are electronically tunable as induced flux is controlled by changing the value of transconductance gain. The Monte-Carlo analysis and temperature analysis have been done and are found to be satisfactory. Simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180 nm CMOS technology parameters. The performance of the proposed meminductor emulator has been verified by embedding theemulator in the design of adaptive learning circuits.

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      Posted on July 25, 2019

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