Articles written in Sadhana
Volume 47 All articles Published: 3 April 2022 Article ID 0065
This paper presents the design, fabrication and packaging of RF MEMS switches that have CPWconverted- to-microstrip RF interface at the die level. With microstrip input and output ports the packaging of the dies become greatly simplified, doing away with the need for having off-chip matching and RF transition components inside the package. Two designs are presented, each based on a different philosophy for conversion of the inherent CPW version of the chip to microstrip planar transmission line; i) conversion to microstripthrough RF matching, ii) CPW to microstrip on-chip via less transition. Detailed 3D EM simulation based studies were carried out to arrive at the final RF layouts. The switches were fabricated using the silicon on glass architecture and packaged in hermetic RF packages at 1 atm N2. Wafer level and post packaging test methods are described. Over the range DC to 10 GHz, the worst case packaged device insertion loss, return loss and isolation are -1.2 dB, -13 dB, -37.5 dB for the first design variant of the switch and are -1.2 dB, -11 dBand -30 dB respectively for the second design variant. The typical pull in voltage is 50 V.