• PRADYUT KUMAR SANKI

      Articles written in Sadhana

    • VLSI implementation of high throughput parallel pipeline median finder for IoT applications

      VASUDEVA BEVARA PRADYUT KUMAR SANKI

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      This paper proposes a high-throughput median finding architecture where the sorting of an incoming pixel is executed by a high-speed Compare and Select (CS) module. In this work, four clock pulses are required to populate the 4 X 4 window as four pixels are read at a time from the incoming grey image. This median finding process is carried out by parallel and pipeline median architecture. The proposed median finding process requires two read operations to take eight input pixels and generates four output pixels with a latency of seven clock cycles. The proposed architecture has been implemented on Xilinx Virtex–VII FPGA. The proposedarchitecture is synthesized using the SoC Encounter along with Faraday 90 nm standard cell library. The maximum operating frequency is 950.57 MHz, the total gate count is 4540, area is 0:40543 mm² and the dissipated power is 0.92617 mW. The high-throughput, high-speed and low-power-dissipation nature of the proposed architecture make it suitable for computationally extensive Internet of Things (IoT) applications.

    • A new fast and efficient 2-D median filter architecture

      VASUDEVA BEVARA PRADYUT KUMAR SANKI

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      Existing architectures for the median filter are based on sorting algorithm where comparators are used in serial. This paper proposes a new high-speed architecture of two dimensional (2-D) median filter where compare and select modules are used in parallel to sort the incoming numbers. The hardware implementation results show that the proposed architecture (PA) operates at 26% and 34% higher frequency in Virtex 4 and Virtex 7 FPGA device, respectively, in comparison with the architectures reported. The PA is synthesized using the RTL Compiler of Cadence along with Faraday 180 nm standard cell library. The maximum operating frequency of the PA is 1.06 GHz with a total gate count of 917. The complete chip layout has been done using the SoC encounter tool. The area of the final chip is 0.13928 mm2 with a power consumption of 0.168 mW analysed using prime-power

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