Parallel and distributed systems play an important part in the improvement of high performance computing. In these type of systems task scheduling is a key issue in achieving high performance of the system. In general, task scheduling problems have been shown to be NP-hard. As deterministic techniques consume much time in solving the problem, several heuristic methods are attempted in obtaining optimal solutions. This paper presents an application of Elitist Non-dominated Sorting Genetic Algorithm (NSGA-II) and a Non-dominated Sorting Particle Swarm Optimization Algorithm (NSPSO) to schedule independent tasks in a distributed system comprising of heterogeneous processors. The problem is formulated as a multi-objective optimization problem, aiming to obtain schedules achieving minimum makespan and flowtime. The applied algorithms generate Pareto set of global optimal solutions for the considered multi-objective scheduling problem. The algorithms are validated against a set of benchmark instances and the performance of the algorithms evaluated using standard metrics. Experimental results and performance measures infer that NSGA-II produces quality schedules compared to NSPSO.

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.