Articles written in Sadhana
Volume 45 All articles Published: 18 August 2020 Article ID 0207
Based on a standard 0.18lm BiCMOS process, a 12 bit 2GSps ADC is achieved using timeinterleaved pipelined architecture in this work. The DC offset caused by the mismatch of ADC channels is removed due to the application of digital calibration technology, which improves the performance of the ADC.The power supply voltage is 1.8 V and the power consumption is 100 mW for each lane. The measurement results indicated that the circuit in this paper can be used in multi-channel time-domain interleaved pipelined ADC architecture to achieve a 2GSps ultra high speed ADC.