Articles written in Sadhana

    • Compact modeling of through silicon vias for thermal analysis in 3-D IC structures


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      Heat mitigation is a major challenge in 3-D IC (Three-Dimensional Integrated Circuit) realization.A study of analytical thermal behavior of the TSV (Through Silicon Via) is very important. Simple and compact yet other models were found deficient to solve this problem in the literature survey. In this paper, resistancenetworks are used to model the heat transfer of the TSVs in both vertical and horizontal directions in simpler and compact models. The accuracy of such models is compared to those from the commercially available CFD(computational fluid dynamics) tool. The errors of corrections between the tool and developed models are corrected by multiplication factors, resulting in 4.18% accuracy. Varying the thicknesses of a liner, filler, soldering, and substrate materials is studied concerning heat transfer and physical behavior of three planar TSV stacked systems. The major purpose is to incorporate both vertical and horizontal thermal resistance networks captured more accurately in heat dissipation paths. Proposed models of TSVs can be used in the active interposersimulations or the face-to-face fabrication stacked methods of the 3-D IC structures.

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