The paper proposes a class-AB flipped voltage follower (FVF) cell, in which the bulk-driven transistor is used as an input transistor with a replica-biased scheme to eliminate the DC level shift while a cascoding transistor is used to reduce the output resistance. The proposed FVF cell has several advantages suchas low output resistance, approximately unity voltage gain, high symmetrical slew rate, high current sourcing capability, high current sinking capability and wide bandwidth. The proposed FVF cell has been simulated inCadence Virtuoso Analog Design Environment using BSIM3v3 180 nm CMOS technology with a power supply voltage of 1.2 V.