• Ashwini Jambhalikar

      Articles written in Sadhana

    • An X band RF MEMS switch based on silicon-on-glass architecture

      M S Giridhar Ashwini Jambhalikar J John R Islam C L Nagendra T K Alex

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      Communication systems such as those used on satellite platforms demand high performance from individual components that make up the varoius systems and sub-systems. Switching and routing of RF signals between various modules is a routine and critical operation that determines the overall efficiency of the entire system. In this paper, we present the design and fabrication aspects of a direct contact RF MEMS switch designed to operate in the X band (8–12 GHz) with a target insertion of about 0·5 dB and isolation better than 30 dB. The actuation voltage is expected to be around 50 V. The die size is designed to be 3 mm (H) × 3 mm(W) × 2 mm(H). The switch is built from a low residual stress device layer of a highly conducting (0·005 Ohms-cm) silicon on insulator (SOI) wafer. After subsequent lithographic steps, the wafer is bonded to a Pyrex glass wafer which has been previously patterned with gold transmission lines and pull in electrodes. Being built from a single crystal silicon structure, the mechanical robustness of the actuator is much greater than the those in similar membrane-based devices. A 6 mask fabrication process utilizing Deep Reactive Ion Etching to achieve high aspect ratio stiction free structures was developed and implemented. Devices from the first fabrication run are being analysed in our laboratory.

    • Design, fabrication, testing and packaging of a silicon micromachined radio frequency microelectromechanical series (RF MEMS) switch

      M S Giridhar Ashwini Jambhalikar Jiju John R Islam Ananda Behera C L Nagendra George Thachil M P Srikanth Shailesh Somani B H M Darukesha Srinivasarao Bollu

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      RF characterization and packaging of a single pole single throw (SPST) direct contact microelectromechanical (MEMS) series radio frequency (RF) switch is reported. Precise thickness of the silicon MEMS structure is achieved using a specially developed silicon Deep Reactive Ion Etching (DRIE) thinning process. A stress free release process is employed which ensures a high yield of released microstructures. The design of the device is based on stiffness equations derived from first principles. Displacement of the actuator under applied field is measured to confirm electrostatic pull in, which occurs in the 30–50 V range. The variation of contact resistance with time has been measured and is found to have a power law decay, in agreement with theoretical models. At the bare die level the insertion loss, return loss and the isolation of the switch were measured to be −0.43 dB, −25 dB and −21 dB, respectively at 10 GHz. The devices were packaged in commercially available RF packages and mounted in alumina boards for post package characterization. Due to the presence of bond wires in the signal path of the packaged devices, the RF performance was found to degrade at high frequencies. However, losses were measured to be at acceptable levels up to 2 GHz. Factors contributing to insertion loss at the die and package device levels are discussed in detail with possible solutions.

    • Design and development of broadband DC-10 GHz packaged RF MEMS switches with on chip CPW-microstrip transitions

      SHAILENDRA SINGH M S GIRIDHAR ASHWINI JAMBHALIKAR T K PRATHEEK AKSHAYA SUPRIYA GOGULAPATI DEEPAK KUMAR SHARMA JIJU JOHN JOLLY DHAR C V N RAO RAJEEV JYOTI SANGAM BHALKE

      More Details Abstract Fulltext PDF

      This paper presents the design, fabrication and packaging of RF MEMS switches that have CPWconverted- to-microstrip RF interface at the die level. With microstrip input and output ports the packaging of the dies become greatly simplified, doing away with the need for having off-chip matching and RF transition components inside the package. Two designs are presented, each based on a different philosophy for conversion of the inherent CPW version of the chip to microstrip planar transmission line; i) conversion to microstripthrough RF matching, ii) CPW to microstrip on-chip via less transition. Detailed 3D EM simulation based studies were carried out to arrive at the final RF layouts. The switches were fabricated using the silicon on glass architecture and packaged in hermetic RF packages at 1 atm N2. Wafer level and post packaging test methods are described. Over the range DC to 10 GHz, the worst case packaged device insertion loss, return loss and isolation are -1.2 dB, -13 dB, -37.5 dB for the first design variant of the switch and are -1.2 dB, -11 dBand -30 dB respectively for the second design variant. The typical pull in voltage is 50 V.

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