Articles written in Sadhana

    • Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications


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      In this paper, a new design of low power, high performance Radix-4 MBW multiplier unit has been described. The low power performance has been achieved by dynamic voltage scaling. Based on CCGDI technique which reduces the switching activity and output capacitance, the proposed multiplier unit has been designed by utilizing three different low power methodologies i.e., reduction in output capacitance and switching activity along with biasing voltage reduction. In order to reduce the number of transistor and delay, here GDI based parallel adders are used in the Wallace tree counters. The multiplier has been implemented with constant threshold voltage PTM 45 nm devices technology and simulated in standard CAD tool simulator for 4, 8 and 16 bit operand multiplications. The proposed design consumes 238.98 lw average power and it has a propagation delay of 2.458 ns for 16 9 16 bit multiplications at speed 100 MBps which is 47% better in terms of power-delay-product than counter based GDI Wallace tree multiplier structure

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