In this paper, a Van der Pol–Duffing (VdPD) jerk oscillator is designed. The proposed VdPD jerk oscillator is built by converting the autonomous two-dimensional VdPD oscillator to a jerk oscillator. Dynamical behaviours of the proposed VdPD jerk oscillator are investigated analytically, numerically and analogically. The numerical results indicate that the proposed VdPD jerk oscillator displays chaotic oscillations, symmetrical bifurcations and coexisting attractors. The physical existence of the chaotic behaviour found in the proposed VdPD jerk oscillator is verified by using Orcad-PSpice software. A good qualitative agreement is shown between thenumerical simulations and the PSpice results. Moreover, the fractional-order form of the proposed VdPD jerk oscillator is studied using stability theorem of fractional-order systems and numerical simulations. It is found that chaos, periodic oscillations and coexistence of attractors exist in the fractional-order form of the proposed jerk oscillator with order less than three. The effect of fractional-order derivative on controlling chaos is illustrated. It is shown that chaos control is achieved in fractional-order form of the proposed VdPD jerk oscillator only for the values of linear controller used. Finally, the problem of drive–response synchronisation of the fractional-order form of the chaotic proposed VdPD jerk oscillators is considered using active control technique.

The control, synchronisation and antisynchronisation of chaos in Josephson junction (JJ) and linear piecewise JJ models via sliding mode control method are investigated in this paper. Thanks to the Routh–Hurwitz stability criterion, the slidingmode controllers are designed to control chaos in JJ models and achieve synchronisation schemes between two non-identical JJ models. Numerical simulations are shown to clarify and confirm the chaos control and synchronisation schemes. Finally, field programmable gate array (FPGA) implementation is designed to reproduce the above-mentioned results and its correctness is confirmed using the FPGA analysis.