Nowadays, the junctionless (JL) multigate (MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are the pacesetter within the emerging nanodevices because of their improved gate-controlling nature [J J Kim and K Roy, IEEE Trans. Electron Devices 51(9), 1468 (2004)] at 20 nm channel node. Here multiple gates are simultaneously controlling the channel. On the other hand, the alignment of the top and bottom gates is a source of worry during fabrication since its effects are detrimental to the performance of the device. Furthermore, with multiple gate-designed DG MOSFETs, the problem of top-to-bottom gate alignment becomes highly significant for the performance of the device. This paper is about an N-doped SiGe DG-JL-MOSFET where a high electron mobility III–V compound GaSb is employed at the source regime. To generate more on-current and low leakage current, SiGe is used for the channel and the drain. Material having high permittivity (HfO$_2$) is used as the gate oxide to enhance the gate controllability at the 20 nm channel node. In this work, the impact of gate misalignment on DC and RF properties of asymmetric double-gate junctionless (ADGJ) and symmetric double-gate junctionless (SDGJ) MOSFETs at 20 nm channel is studied using simulations. The influence of gate underlap and overlap on several DC and RF characteristics such as I$_d$V$_g$, I$_d$V$_d$, g$_m$, g$_d$, intrinsic gain, C$_{gs}$, C$_{gd}$ and f$_T$ are discussed in this manuscript, and it is observed that the DG-JL-MOSFET shows a better response to DC and RF characteristics for 50% of the gate misalignment towards the source. In the proposed structure, an improvement in drain current is observed during the misalignment of the front gate towards the source. The value of I$_{on}$/I$_{off}$ is also more in the caseof the proposed heterostructure device than the earlier Si-based JLFET.