The paper presents a drain current model for double gate metal oxide semiconductor field effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for short-channel velocity saturation effect independently in the front and the back gate controlled channels under asymmetric front and back gate bias and oxide thickness. To determine the front and the back-channel velocity saturation, drain-induced barrierlowering is evaluated by effective gate voltages at the front and back gates obtained from surface potential at the threshold condition after considering symmetric and asymmetric front and back oxide thickness. The model alsoincorporates surface roughness scattering and ionized impurity scattering to estimate drain current for heavily/lightly doped channel for short-channel asymmetric DG MOSFET and a good agreement has been achieved with TCADsimulations, with a relative error of around 3–7%.

An aluminium gallium nitride/gallium nitride ($\rm{Al_{0.3}Ga_{0.7}N/GaN}$) high electron mobility transistor (HEMT) is designed at a gate length ($L_{G}$) of 0.1 $\mu$m, drain-to-source spacing ($L_{SD}$) of 3 $\mu$m and drain length to source length ratio ($L_{D}:L_{S}$) of 1. The HEMT is investigated by considering four different heterostructures, namely single channel, single channel with back-barrier, double channel and double channel with back-barrier. A two-dimensional electron gas (2DEG) is formed at the interface of AlGaN/GaN HEMT (DC HEMT). The physical importance of indium gallium nitride (InGaN) as back-barrier is to increase carrier confinement by raising the conduction band of GaN buffer. The double-channel HEMT (DC HEMT) with back-barrier shows the highest current drive. There is an improvement of 3.16% in drain current and an improvement of 4.58% in cut-off frequency at a gate-to-source voltage of −0.5 V for the DC HEMT with back-barrier compared to the DC HEMT without back-barrier. For further improvement in transconductance and cut-off frequency, the structure of DC HEMT with back-barrier is modified by increasing the drain contact length and decreasing the source contact length, that is $L_{D}:L_{S} = 3$, keeping the drain-to-source spacing unchanged, i.e. $L_{SD} = 3 \mu m$. There is 32.55% improvement in transconductance and 14.03% improvement in cut-off frequency at a gate-to-source voltage of −0.5 V for the DC HEMT with back-barrier at $L_{D}:L_{S} = 3$ compared to the DC HEMT with back-barrier at $L_{D}:L_{S} = 1$.

Nowadays, the junctionless (JL) multigate (MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are the pacesetter within the emerging nanodevices because of their improved gate-controlling nature [J J Kim and K Roy, IEEE Trans. Electron Devices 51(9), 1468 (2004)] at 20 nm channel node. Here multiple gates are simultaneously controlling the channel. On the other hand, the alignment of the top and bottom gates is a source of worry during fabrication since its effects are detrimental to the performance of the device. Furthermore, with multiple gate-designed DG MOSFETs, the problem of top-to-bottom gate alignment becomes highly significant for the performance of the device. This paper is about an N-doped SiGe DG-JL-MOSFET where a high electron mobility III–V compound GaSb is employed at the source regime. To generate more on-current and low leakage current, SiGe is used for the channel and the drain. Material having high permittivity (HfO$_2$) is used as the gate oxide to enhance the gate controllability at the 20 nm channel node. In this work, the impact of gate misalignment on DC and RF properties of asymmetric double-gate junctionless (ADGJ) and symmetric double-gate junctionless (SDGJ) MOSFETs at 20 nm channel is studied using simulations. The influence of gate underlap and overlap on several DC and RF characteristics such as I$_d$V$_g$, I$_d$V$_d$, g$_m$, g$_d$, intrinsic gain, C$_{gs}$, C$_{gd}$ and f$_T$ are discussed in this manuscript, and it is observed that the DG-JL-MOSFET shows a better response to DC and RF characteristics for 50% of the gate misalignment towards the source. In the proposed structure, an improvement in drain current is observed during the misalignment of the front gate towards the source. The value of I$_{on}$/I$_{off}$ is also more in the caseof the proposed heterostructure device than the earlier Si-based JLFET.