Articles written in Pramana – Journal of Physics

    • Impact of gate-on-source misalignment on the analog and digital performance of tunnel FET


      More Details Abstract Fulltext PDF

      The tunnel FET (TFET) is considered a promising candidate which can be used in the design of digital and analog circuits in low-power applications. Due to fabrication tolerances, it is not guaranteed that the gate electrode is perfectly aligned on the channel, especially for short channel structures. In this work, we investigate the effect of gate misalignment towards the source by using TCAD simulations. The proposed structure is presented in which a low-k dielectric pocket is inserted above the source and beneath the high-k gate oxide to mitigate the undesirable impact of gate misalignment. We show that the insertion of a silicon dioxide (SiO$_2$) pocket above the source enhances the DC performance (in terms of ON/OFF ratio, threshold voltage and subthreshold swing (SS)), RF performance (in terms of cut-off frequency) and it also improves the transient response of the inverter circuits.

    • Impact of gate-on-drain overlap on the electrical characteristics of TFETs: Role of oxide material and drain spacer


      More Details Abstract Fulltext PDF

      In the current study, the gate overlap on the drain side was investigated from the prospects of both DC and high-frequency behaviour. The key parameters extracted in this work to determine the main performance parameters are subthreshold swing (SS), ambipolar current (I$_{amb}$), ON/OFF current ratio and cut-off frequency. Although the gate overlap on the drain decreases the ambipolar current, it has an adverse effect on the high-frequency performance as the gate-to-drain capacitance increases. This behaviour is observed for increasing overlap length for low-k gate oxide. On the other hand, the ambipolar current does not show a considerable decline when using high-k gate oxide. To obtain a low ambipolar current at lower values of equivalent oxide thickness (EOT), we propose a low-k dielectric spacer above the drain side. The low-k spacer not only decreases the gate-to-drain capacitance butalso facilitates the suppression of ambipolarity due to overlap. All simulations carried out in this work are done using the Silvaco TCAD device simulator.

  • Pramana – Journal of Physics | News

    • Editorial Note on Continuous Article Publication

      Posted on July 25, 2019

      Click here for Editorial Note on CAP Mode

© 2022-2023 Indian Academy of Sciences, Bengaluru.