Articles written in Pramana – Journal of Physics

    • Influence of structural and doping parameter variations on Si and $\rm{Si_{1−x} Ge_{x}}$ double gate tunnel FETs: An analysis for RF performance enhancement


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      This paper deals with the effect of structural and doping parameter variations on RF parameters for Si and $\rm{Si_{1−x}Ge_{x}}$ -based double gate (DG) tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. The DC parameter subthreshold swing (SS) and RF parameter metrics, unity gain cut-off frequency ($f_{t}$) and maximum oscillation frequency ($f_{max}$) are extracted by varying structural parameters, gate length ($L_{g}$), gate oxide thickness ($t_{ox}$), channel thickness ($t_{ch}$), doping parameters, channel doping ($N_{ch}$), drain doping ($N_{d}$) and source doping ($N_{s}$) in and around their nominal value. For a channel thickness of 15 nm, a very less SS of 8 mV/dec is achieved in $\rm{Si_{1−x}Ge_{x}}$ -based DG TFETs with gate-drain overlap. Variations of gate oxide thickness offer better RF performance enhancement for Si-based asymmetric gate oxide devices. This could be achieved because of the higher tunnelling rate of electrons occurring at the source side of asymmetric gate oxide devices.

    • A family of conservative chaotic systems with cyclic symmetry


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      In this paper, we propose a family of circulant systems with conservative property. Various dynamical properties of the circulant systems are derived and investigated. Bifurcation plots are derived and presented for a system and the Lyapunov exponents are derived to show the existence of chaotic oscillations, and their sum being zero confirms the conservativeness for certain values of parameters. One of the proposed systems is then implemented in field programmable gate array (FPGA) to show the hardware reliability. We used the hardware–software cosimulation to see the phase portraits of the FPGA implemented system. The discrete integrators required for solving the initial value problem are implemented using the Euler’s method. The register transfer level schematics of the FPGA implemented system and the resources used for the implementations are presented.

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