This paper presents high-performance computing efforts with FPGA for the accelerated pulsar/transient search for the square kilometre array (SKA). Case studies are presented from within SKA and pathfinder telescopes highlighting future opportunities. It reviews the scenario that has shifted from offline processing of the radio telescope data to digitizing several hundreds/thousands of antenna outputs over huge bandwidths, forming several hundreds of beams, and processing the data in the SKA real-time pulsar search pipelines. A briefaccount of the different architectures of the accelerators, primarily, the new generation field programmable gate array-based accelerators, showing their critical roles to achieve high-performance computing and in handlingthe enormous data volume problems of the SKA is presented here. It also presents power-performance efficiency of this emerging technology and presents potential future scenarios.

Backed by advances in digital electronics, signal processing, computation and storage technologies, aperture arrays, which had strongly influenced the design of telescopes in the early years of radio astronomy, havemade a comeback. Amid all these developments, an international effort to design and build the world’s largest radio telescope, the Square Kilometre Array (SKA), is ongoing. With its vast collecting area of 1 km$^2$, the SKA is envisaged to provide unsurpassed sensitivity and leverage technological advances to implement a complex receiver to provide a large field of view through multiple beams on the sky. Many pathfinders and precursor aperture array telescopes for the SKA, operating in the frequency range of 10–300 MHz, have been constructed and operationalized to obtain valuable feedback on scientific, instrumental and functional aspects. This review article looks explicitly into the progression of digital-receiver architecture from the Murchison Widefield Array(precursor) to the SKA1-Low. It highlights the technological advances in analog-to-digital converters (ADCs), field-programmable gate arrays (FPGAs) and central processing unit–graphics processing unit (CPU–GPU) hybrid platforms around which complex digital signal processing systems implement efficient channelizers, beamformers and correlators. The article concludes with a preview of the design of a new generation signal processing platform based on radio frequency system-on-chip (RFSoC).