Simultaneous optimization of the area, wirelength and TSVs in a 3D IC design
Click here to view fulltext PDF
The technology of a three-dimensional integrated circuit (3D-IC) is an emerging approach for improving performance. In comparison to a standard 2-D IC design, which arranges all of the devices on a single planar layer, a 3D-IC stacking of many tiers enables more devices to be placed close together, resulting in a significant area and wirelength reduction. Designing a 3D-IC introduces an extra parameter to be considered while assigning a layer to any circuit component where different layers are connected Through Silicon Vias. Inthis paper, we have applied the Parallel-PSO approach to optimize the area, wirelength of the layout and the number of TSVs to connect the different layers simultaneously. The results are obtained and compared with the benchmark circuits available with MCNC and GSRC.
ATUL PRAKASH1 RAJESH KUMAR LAL2
Volume 48, 2023
Continuous Article Publishing mode
Click here for Editorial Note on CAP Mode