Internet of things (IoT) connects a huge number of small devices across a network. End-to-end security is becoming highly crucial as IoT deploys these devices. In this paper, two hardware architectures for CLEFIA cipher are proposed that are capable of providing robust security to encrypt image input under resource-constrained IoT applications. The proposed round-based and pipelined implementations yield better throughput for high-speed applications. In addition, the proposed round-based and pipelined architectures improve maximum operating frequency by 52.95% and 117.22% for Artix-7 FPGA family. The ASIC implementation results show a 39.22% and 51.92% improvement in hardware efficiency over state-of-the-art design, respectively. Moreover, these proposed architectures have been utilized to encrypt images by selecting variable tile sizes along with the control unit. This paper also explores the security of images encrypted by the proposed hardware architecture of the CLEFIA cipher. The existing solutions were compared to correlation coefficients,NPCR, UACI, MSE, PSNR and entropy values.