• Comparative analysis of Yavadunam Tavadunikrtya Varganca Yojayet Vedic multiplier for embedded DNN

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    • Keywords


      Vedic multiplier; Yavadunam sutra; multiplication; bit reduction technique; Vedic mathematics; binary multiplier.

    • Abstract


      Memory and computationally efficient CNNs for mobile and embedded applications have sparked a lot of interest recently. Depth-wise and point-wise convolutions are used in MobileNet. In this paper, a Vedic multiplier based on the Yavadunam sutra is used to reduce hardware resource utilization at all design stages in efficient computational kernels, data pruning, memory compression, and quantization to manage the huge computation and storage difficulties of DNNs. Using the teachings of Vedic math, this multiplier will yield ahigher propagation speed, lower computational complexity, reduced propagation delay, and less power consumption than multipliers based on the principles of classical mathematics. A multiplier is a critical component in Digital Signal Processing DSP frameworks, which are key components in the majority of computationally advanced frameworks. As a result, the speed and power utilization of multipliers are two critical parameters. The Vedic multiplier presented in this paper is commonly used to find decimal number squares and cubes. By modifying the existing sutra for binary numbers with the bit reduction technique, the hardware design of the Yavadunam Vedic sutra is proposed. The proposed Vedic multiplier was written in VHDL, which stands for Very High Speed Integrated Circuits Hardware Description Language. On the Spartan FPGA board, the multiplier was implemented using the Xilinx Tool and the system generator instrument. The computational complexity and propagation delay of the Vedic multiplier were lower than those of a regular multiplier.

    • Author Affiliations



      1. Department of ECE, Sasurie College of Engineering, Tirupur, India
      2. KSR College of Engineering, Tamil Nadu, Namakkal, India
    • Dates

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