The voltage level converters (LCs) are required to attain optimized power consumption by interfacing two or more supply voltage domains in Systems-on-Chip (SoC) applications. The voltage level-up conversion can be easily and effectively achieved by the use of buffer structures. Hence this article proposes two buffer-based LCs, namely transmission gate buffer level converter (TGBLC) and stacked PMOS buffer level converter (SPBLC), based on voltage stepping technique. The energy-efficient transmission gate (TG) and stacked PMOS (SP) structures are proposed to define voltage steps in the buffer and ensure a wider voltage conversion range with high speed. The LCs are implemented in 0.18 lm technology and their performance metrics are verified using a Spectre circuit simulator. The simulation results show that TGBLC and SPBLC can convert a low input voltage of 600 and 550 mV to 1.8 V, respectively. For the target input voltage of 0.8 V with frequency of 1 MHz, the TGBLC and SPBLC exhibit an improved delay of 7.3 and 7.1 ns with an energy consumption of 9.66 and 6.66 pJ per transition, respectively. It is noted from the experimental results that theproposed LCs are suitable for applications where simplicity and energy efficiency/low power with a wider conversion range is preferred.