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      Permanent link:
      https://www.ias.ac.in/article/fulltext/sadh/045/0207

    • Keywords

       

      Time-interleaved; DC offset; digital calibration; pipelined ADC.

    • Abstract

       

      Based on a standard 0.18lm BiCMOS process, a 12 bit 2GSps ADC is achieved using timeinterleaved pipelined architecture in this work. The DC offset caused by the mismatch of ADC channels is removed due to the application of digital calibration technology, which improves the performance of the ADC.The power supply voltage is 1.8 V and the power consumption is 100 mW for each lane. The measurement results indicated that the circuit in this paper can be used in multi-channel time-domain interleaved pipelined ADC architecture to achieve a 2GSps ultra high speed ADC.

    • Author Affiliations

       

      HAO ZHANG HONGLIN XU1 YICHEN FAN XIAOMING XING HAITAO LIU JUNJIE WU

      1. Nanjing Research Institute of Electronics Technology, Nanjing 210000, China
    • Dates

       
  • Sadhana | News

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