• Resolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitors

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      https://www.ias.ac.in/article/fulltext/sadh/045/0184

    • Keywords

       

      ADC; SAR; SC; area-efficient SAR; non-binary; OTA

    • Abstract

       

      A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitorsfor a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardwareoverhead.

    • Author Affiliations

       

      KALPANA G BHAT1 T LAXMINIDHI M S BHAT

      1. Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal 575025, India
    • Dates

       
  • Sadhana | News

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