• VLSI implementation of high throughput parallel pipeline median finder for IoT applications

    • Fulltext

       

        Click here to view fulltext PDF


      Permanent link:
      https://www.ias.ac.in/article/fulltext/sadh/045/0075

    • Keywords

       

      Low latency; compare and select module; parallel median filter; pipeline median filter; ASIC design.

    • Abstract

       

      This paper proposes a high-throughput median finding architecture where the sorting of an incoming pixel is executed by a high-speed Compare and Select (CS) module. In this work, four clock pulses are required to populate the 4 X 4 window as four pixels are read at a time from the incoming grey image. This median finding process is carried out by parallel and pipeline median architecture. The proposed median finding process requires two read operations to take eight input pixels and generates four output pixels with a latency of seven clock cycles. The proposed architecture has been implemented on Xilinx Virtex–VII FPGA. The proposedarchitecture is synthesized using the SoC Encounter along with Faraday 90 nm standard cell library. The maximum operating frequency is 950.57 MHz, the total gate count is 4540, area is 0:40543 mm² and the dissipated power is 0.92617 mW. The high-throughput, high-speed and low-power-dissipation nature of the proposed architecture make it suitable for computationally extensive Internet of Things (IoT) applications.

    • Author Affiliations

       

      VASUDEVA BEVARA1 PRADYUT KUMAR SANKI1

      1. Department of ECE, SRM University-AP, Guntur, India
    • Dates

       
  • Sadhana | News

    • Editorial Note on Continuous Article Publication

      Posted on July 25, 2019

      Click here for Editorial Note on CAP Mode

© 2021-2022 Indian Academy of Sciences, Bengaluru.