• A new universal gate for low power SoC applications

    • Fulltext


        Click here to view fulltext PDF

      Permanent link:

    • Keywords


      Low power; CMOS; pass-transistor; NAND gate; Koomey’s law.

    • Abstract


      This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels.

    • Author Affiliations


      M Geetha Priya1 K Baskaran2

      1. Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham, Coimbatore 641 112, India
      2. Department of Computer Science and Engineering, Government College of Technology, Coimbatore 641 013, India
    • Dates


© 2017-2019 Indian Academy of Sciences, Bengaluru.