• Impact of gate-on-source misalignment on the analog and digital performance of tunnel FET

• # Fulltext

https://www.ias.ac.in/article/fulltext/pram/095/0124

• # Keywords

Tunnel field effect transistor; low-k dielectric pocket; subthreshold swing; ON/OFF ratio; cut-off frequency

• # Abstract

The tunnel FET (TFET) is considered a promising candidate which can be used in the design of digital and analog circuits in low-power applications. Due to fabrication tolerances, it is not guaranteed that the gate electrode is perfectly aligned on the channel, especially for short channel structures. In this work, we investigate the effect of gate misalignment towards the source by using TCAD simulations. The proposed structure is presented in which a low-k dielectric pocket is inserted above the source and beneath the high-k gate oxide to mitigate the undesirable impact of gate misalignment. We show that the insertion of a silicon dioxide (SiO$_2$) pocket above the source enhances the DC performance (in terms of ON/OFF ratio, threshold voltage and subthreshold swing (SS)), RF performance (in terms of cut-off frequency) and it also improves the transient response of the inverter circuits.

• # Author Affiliations

1. Engineering Physics and Mathematics Department, Faculty of Engineering, Ain Shams University, Cairo, Egypt
2. Communication and Information Engineering Department, University of Science and Technology, Zewail City, Giza, Egypt
3. Electronics and Communications Department, Faculty of Engineering, Arab Academy for Science, Technology and Maritime Transport, Cairo, Egypt
4. Canadian Higher Institute for Engineering, 6th October, Canadian International College (CIC), Cairo, Egypt

• # Pramana – Journal of Physics

Volume 96, 2022
All articles
Continuous Article Publishing mode

• # Editorial Note on Continuous Article Publication

Posted on July 25, 2019