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      https://www.ias.ac.in/article/fulltext/pram/089/02/0033

    • Keywords

       

      Asymmetric double gate; drain current; drain-induced barrier lowering; velocity saturation; drain saturation voltage

    • Abstract

       

      The paper presents a drain current model for double gate metal oxide semiconductor field effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for short-channel velocity saturation effect independently in the front and the back gate controlled channels under asymmetric front and back gate bias and oxide thickness. To determine the front and the back-channel velocity saturation, drain-induced barrierlowering is evaluated by effective gate voltages at the front and back gates obtained from surface potential at the threshold condition after considering symmetric and asymmetric front and back oxide thickness. The model alsoincorporates surface roughness scattering and ionized impurity scattering to estimate drain current for heavily/lightly doped channel for short-channel asymmetric DG MOSFET and a good agreement has been achieved with TCADsimulations, with a relative error of around 3–7%.

    • Author Affiliations

       

      PRADIPTA DUTTA1 BINIT SYAMAL2 KALYAN KOLEY3 ARKA DUTTA3 C K SARKAR3

      1. School of Technology, Electronics and Telecommunication Engineering, KIIT University, Bhubaneswar 751 024, India
      2. School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
      3. Nano Device Simulation Lab, Department of Electronics and Communication Engineering, Jadavpur University, Kolkata 700 032, India
    • Dates

       
  • Pramana – Journal of Physics | News

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