This paper describes the fabrication of MOS capacitor and DLTS study of annihilation of deeplevel defects upon thermal annealing. Ni/SiO2/𝑛-Si MOS structures fabricated on 𝑛-type Si wafers were investigated for process-induced deep-level defects. The deep-level traps in Si substrates induced during the processing of Ni/SiO2/𝑛-Si have been investigated using deep-level transient spectroscopy (DLTS). A characteristic deep-level defect at 𝐸C = 0.49 eV which was introduced during high-temperature thermal oxidation process was detected. The trap position was found to shift to different energy levels (𝐸C = 0.43, 0.46 and 0.34 eV) during thermal annealing process. The deep-level trap completely anneals at 350°C. Significant reduction in trap density with an increase in recombination life time and substrate doping concentration as a function of isochronal annealing were observed.
Volume 45, 2022
Continuous Article Publishing mode
Prof. Subi Jacob George — Jawaharlal Nehru Centre for Advanced Scientific Research, Jakkur, Bengaluru
Chemical Sciences 2020
Prof. Surajit Dhara — School of Physics, University of Hyderabad, Hyderabad
Physical Sciences 2020
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