• Fulltext

       

        Click here to view fulltext PDF


      Permanent link:
      https://www.ias.ac.in/article/fulltext/boms/034/07/1627-1631

    • Keywords

       

      MOS capacitor; DLTS; deep-level defect; thermal annealing.

    • Abstract

       

      This paper describes the fabrication of MOS capacitor and DLTS study of annihilation of deeplevel defects upon thermal annealing. Ni/SiO2/𝑛-Si MOS structures fabricated on 𝑛-type Si wafers were investigated for process-induced deep-level defects. The deep-level traps in Si substrates induced during the processing of Ni/SiO2/𝑛-Si have been investigated using deep-level transient spectroscopy (DLTS). A characteristic deep-level defect at 𝐸C = 0.49 eV which was introduced during high-temperature thermal oxidation process was detected. The trap position was found to shift to different energy levels (𝐸C = 0.43, 0.46 and 0.34 eV) during thermal annealing process. The deep-level trap completely anneals at 350°C. Significant reduction in trap density with an increase in recombination life time and substrate doping concentration as a function of isochronal annealing were observed.

    • Author Affiliations

       

      N Shashank1 Sanjeev K Gupta2 K V Madhu3 J Akhtar2 R Damle3

      1. Department of Electronics, Kuvempu University, Shankaraghatta 577 451, India
      2. Sensors and Nanotechnology Group, Central Electronics Engineering Research Institute, Pilani 333 031, India
      3. Department of Physics, Bangalore University, Bangalore 560 056, India
    • Dates

       
  • Bulletin of Materials Science | News

    • Editorial Note on Continuous Article Publication

      Posted on July 25, 2019

      Click here for Editorial Note on CAP Mode

© 2017-2019 Indian Academy of Sciences, Bengaluru.